1. Field of the Invention
The present invention relates to the determining of electrical parameters of semiconductor devices, and in particular to a method for determining electrical parameters of semiconductor devices by exposing them to a corona discharge.
2. Description of the Prior Art
A large portion of long-term electrical failures of semiconductor devices and integrated circuits is due to surface electrical mechanisms. These surface mechanisms include contaminant sodium ion migration, moisture enhanced surface conductivity of passivating layers, and electrical instability at elevated temperatures of plastic coating or encapsulating materials. Elimination of these mechanisms, while possible, is not assured in any given device or circuit.
The manner in which these surface electrical mechanisms affect devices is by electrical field effect action on the underlying semiconductor surfaces. In simple cases, it is possible to minimize effects of surface electrical sensitivity, for example, by using diffused guard rings or "channel stops" to break shunting channel paths on device surfaces or by placing metal field plates over junction edges to act as electrostatic shields. In more complex units, such design approaches may be too wasteful of space or may introduce undesirable parasitic capacitances. As a result, the inherent surface electrical sensitivity of devices or circuits can be widely variable. There are corresponding variations and propensity to device or circuit failure even for identical conditions of surface failure mechanisms. Even in the case of simple transistors, devices from one supplier may exhibit significant degradation in important electrical parameters, such as the common emitter current gain as a result of electrical stress at high temperatures in the presence of surface contaminants, while those from another supplier may be quite stable.
Clearly, a method of assessing the surface sensitivity of semiconductor devices and circuits has useful application. For the user, it could allow selection of the least surface sensitive units when several sources are available. For a manufacturer, it might allow segregating units of a given type according to degree of sensitivity. Less sensitive units could be marketed for applications demanding more reliability.
To date, only indirect methods have been used to assess surface electrical sensitivity of complex semiconductor products, generally without separating failure due to electrical surface sensitivity from failure due to surface electrical mechanisms. Usually, semiconductor devices are subjected in sufficient numbers to stress testing, for example, electrical bias at elevated temperature or humidity, for prolonged periods of time, for example, 100 hours to 1000 hours. Failures to perform within specified limits are analyzed statistically.
The tests may be used to screen out unacceptable units or to qualify an entire lot from which the test sample was selected. Results for tests of longer duration may be used to estimate failure rates for the units in use. Such approaches can be costly and time consuming. Since they do not separate surface sensitivity from failure of mechanisms such as ion or moisture contamination, the results are only valid for the conditions of a given test population. Such results are often misapplied when low failure rates are indicated, as being characteristic of particular vendors or fabrication technologies.
Since surface electrical failure in use occurs through field effect means, it is desirable to have a method using these means to characterize the surface electrical sensitivity of completed semiconductor products of any given type, before final encapsulation. It is desirable that this can be done without using special test structures on the product and without altering the design or fabrication of the product in order to minimize the particular costs associated with the method.
Corona charging of uniform insulator surfaces on uniformly-doped semiconductor pieces has been used as a tool to study ion migration and electronic conduction in insulator films. In particular, a corona charging method is discussed in Woods, et al, "Injection and Removal of Ionic Charge at Room Temperature Through the Interface of Air with SiO.sub.2 ", Journal of Applied Physics, Vol. 44, No. 12, December 1973; Woods et al, "Mobile Fluoride Ions in SiO.sub.2 ", Journal of Applied Physics, Vol. 46, No. 2, February 1975; and Weinberg, "Hole Injection and Transport in SiO.sub.2 Films on Si", Applied Physics Letters, Vol. 27, No. 8, 15 October 1975. In the above articles, no device structures were formed in the silicon substrates, consequently, there was no attempt to use corona charging for the purposes of changing the electrical conditions at the semiconductor surfaces.
In addition, it is clear that semiconductor devices which are electrically sensitive to surface effects can be optimized in some aspect of their electrical behavior if the electric field normal to the device surface can be controllably adjusted. Such optimization is of practical significance if permanent electric field adjustment is possible.
With the development of metal-oxide-semiconductor (MOS) technology, it has been possible to use thin film insulated (TFI) metal field plates for controlling the electric field at semiconductor surfaces. Such a method is shown and discussed in Grove, "Physics and Technology of Semiconductor Devices", FIGS. 10.12 and 10.13, pages 303-304, John Wiley & Sons, Inc., New York (1967). Although TFI metal field plates may be used in some special devices, this approach is not widely used in commercial devices for a number of reasons. Among these are: (1) the spaced required for field plates may not be available in densely packed circuits; (2) the finite dimensions of the field plates may produce undesirable electric field enhancement at their edges; (3) the field plates may introduce undesirable parasitic capacitances; (4) for greatest flexibility, an external biasing terminal is required for each field plate; (5) internally grounded field plates may be used to reduce surface sensitivity but they do not permit optimal surface field control; (6) field plates must be designed into device or circuit structures, their addition to otherwise desirable products could be cumbersome; (7) field plates are not readily prepared on nonplanar, i.e., mesa surfaces; (8) for optically sensitive devices, special technologies are required for either thin metal or conducting oxide field plates.
Another approach to controlling surface electric fields is possible, in principle, by adjusting the charge associated with the passivating dielectric layers applied to the device surfaces. For thermally grown SiO.sub.2 on silicon, the net insulator charge density, as determined using MIS structures, is a function of processing parameters including moisture content of the oxidizing ambient, the temperature of growth, and the cooling rate, as discussed in the above-referenced Grove text at page 343, FIG. 12.8. This is not a particularly practical approach to controlling surface behavior. In devices requiring complex fabrication, the ability to finely control insulator charge by these means is lost.
Even if processing controls with thermally grown oxides were sufficiently practical, the insulator charge is always positive in sign, thus precluding adjustment of surface fields when negative charge is needed. Other insulator deposition techniques, such as reactive sputtering, can produce films having charge of both polarities as discussed in Wu and Formigoni, "Charge Phenomena in dc Reactively Sputtered SiO.sub.2 Films", Journal of Applied Physics, Vol. 39, No. 12, November 1968. Such processes have not been widely applied to silicon device or integrated circuit fabrication, suffering as does thermal oxidation, from the inability to finely control charge effects during complex fabrication steps. A method is needed to adjust the surface electric field in semiconductor devices having insulating films on their surfaces while avoiding the disadvantages detailed above in reference to the TFI field-plate method of surface field control. This method should include the ability to finely control charge effects during complex fabrication steps.